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Applications Information
Input Thresholds
The FAN3268 driver has TTL input thresholds and
provides buffer and level translation functions from logic
inputs. The input thresholds meet industry-standard
TTL-logic thresholds, independent of the V DD voltage,
and there is a hysteresis voltage of approximately 0.4 V.
V DD
These levels permit the inputs to be driven from a range
of input logic signal levels for which a voltage over 2 V
is considered logic high. The driving signal for the TTL
inputs should have fast rising and falling edges with a
slew rate of 6 V/μs or faster, so a rise time from 0 to
3.3 V should be 550 ns or less. With reduced slew rate,
circuit noise could cause the driver input voltage to
exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation.
Input
stage
V OUT
Static Supply Current
In the I DD (static) typical performance characteristics
(see Figure 6) , the curve is produced with all inputs /
enables floating (OUT is low) and indicates the lowest
static I DD current for the tested configuration. For other
states, additional current flows through the 100 k ?
resistors on the inputs and outputs shown in the block
diagram ( see Figure 3) . In these cases, the actual static
I DD current is the value obtained from the curves plus
this additional current.
MillerDrive? Gate Drive Technology
FAN3268 gate drivers incorporate the MillerDrive?
architecture shown in Figure 1. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between one and two
thirds V DD and the MOS devices pull the output to the
high or low rail.
The purpose of the MillerDrive? architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications with zero voltage switching during the
MOSFET turn-on or turn-off interval, the driver supplies
high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs
in synchronous rectifier applications because the body
diode is generally conducting before the MOSFET is
switched on.
The output pin slew rate is determined by V DD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall
time at the MOSFET gate is needed.
? 2009 Fairchild Semiconductor Corporation
FAN3268 ? Rev. 1.0.3
12
Figure 27. MillerDrive? Output Architecture
Under-Voltage Lockout
Internal circuitry provides an under-voltage lockout
function that prevents the output switching devices from
operating if the V DD supply voltage is below the
operating level. When V DD is rising, but below the 3.9 V
operational level, internal 100 k ? resistors bias the non-
inverting output low and the inverting output to V DD to
keep the external MOSFETs off during startup intervals
when logic control signals may not be present. After the
part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent
chatter when low V DD supply voltages have noise from
the power switching.
V DD Bypass Capacitor Guidelines
To enable this IC to turn a device on quickly, a local high-
frequency bypass capacitor C BYP with low ESR and ESL
should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to
bulk electrolytic capacitance of 10 μF to 47 μF commonly
found on driver and controller bias circuits.
A typical criterion for choosing the value of C BYP is to
keep the ripple voltage on the V DD supply to ≤5%. This
is often achieved with a value ≥20 times the equivalent
load capacitance C EQV , defined here as Q GATE /V DD .
Ceramic capacitors of 0.1 μF to 1 μF or larger are
common choices, as are dielectrics, such as X5R and
X7R, with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
C BYP may be increased to 50-100 times the C EQV or
C BYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the C BYP would be twice as large as when
a single channel is switching.
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